site:semiengineering.com

Research Bits: Jan. 27

Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory ...

Semiconductor Engineering

Semiconductor Supply Chain Security Using Side-Channel Power Measurements and Generative Adversarial Networks (Cornell)

Band Power Side-Channel Detection for Semiconductor Supply Chain Integrity at Scale” was published by researchers at Cornell ...

Semiconductor Engineering

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)

A new technical titled “Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications” was published by researchers ...

Semiconductor Engineering

Balancing Training, Quantization, And Hardware Integration In NPUs

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures ...

Semiconductor Engineering

Hypergraph-based Techniques To Map Spiking Neural Networks on Neuromorphic HW (Politecnico di Milano)

A new technical paper titled “A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware” was published by ...

Semiconductor Engineering

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (imec, Hanyang Univ.)

A new technical paper titled “Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement ...

Semiconductor Engineering

Outlier-aware Quantization Framework Co-designed With Heterogeneous NVM For SLM Deployment on Edge Platforms (UCSD et al.)

Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design” was published by researchers at ...

Semiconductor Engineering

Show inaccessible results

Research Bits: Jan. 27

Semiconductor Supply Chain Security Using Side-Channel Power Measurements and Generative Adversarial Networks (Cornell)

MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)

Balancing Training, Quantization, And Hardware Integration In NPUs

Hypergraph-based Techniques To Map Spiking Neural Networks on Neuromorphic HW (Politecnico di Milano)

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (imec, Hanyang Univ.)

Outlier-aware Quantization Framework Co-designed With Heterogeneous NVM For SLM Deployment on Edge Platforms (UCSD et al.)

Better Contact Resistance in Top-Gate CNFETs through Self-Aligned MoOx Nanoparticle Contact Doping (NYCU et al.)

Confidentiality-preserving Framework For Secure On-Chip Communication in NoC Architectures

Overview and Comparison of Devices Used For Optical Waveguide-to-Waveguide Coupling (MIT et al.)

A Verification Framework For Trojan Detection (U. of Kansas, U. of Florida)

Ripple Effects: Why Water Risk Is The Next Major Business Challenge For The Semiconductor Industry