Semiconductor Engineering5h
Research Bits: Oct. 1
Rust-resistant coating for 2D semiconductors; polymeric material for data storage and encryption; quantum-secure deep ...
Semiconductor Engineering1d
Data Routing In Heterogeneous Chip Designs
Ensuring data gets to where it’s supposed to go at exactly the right time is a growing challenge for design engineers and ...
Semiconductor Engineering5d
UMI Can Scale the Memory Wall
UMI to OCP as an extension to the BoW standard. While the improvements in processor performance to enable the incredible ...
Semiconductor Engineering5d
Using AI To Glue Disparate IC Ecosystem Data
Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need to ...
Semiconductor Engineering6d
Optimizing Wafer Edge Processes For Chip Stacking
Several critical processes address wafer flatness, wafer edge defects and what's needed to enable bonded wafer stacks.
Semiconductor Engineering4d
Dualtronics: Photonic Devices on the Cation Face and Electronic Devices on the Anion Face of the Same Wafer
A new technical paper titled “Using both faces of polar semiconductor wafers for functional devices” was published by ...
Semiconductor Engineering3d
Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
A new technical paper titled “Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs” was ...
Semiconductor Engineering4d
Hardware Acceleration Approach for KAN Via Algorithm-Hardware Co-Design
A new technical paper titled “Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference” was ...
Semiconductor Engineering3d
Memristors: Flexible Behavioral Model ( Israel Institute of Technology)
A Compact Behavioral Model for Volatile Memristors” was published by researchers at Technion – Israel Institute of Technology ...
Semiconductor Engineering5d
Pressure Builds To Adopt Virtual Prototypes
Creating complex multi-chiplet systems is no longer a back-of-the-envelope diagram, but viable methodologies are still in ...
Semiconductor Engineering6d
Blog Review: Sept. 25
PCIe 6.1 flow control; formal basics; cloud EDA boosts time to market; testing PCB interconnects with boundary scan; ...
Semiconductor Engineering4d
Chip Industry Week In Review
Global spending on 300mm fab equipment is expected to reach a record US$400 billion from 2025 to 2027, according to SEMI. Key drivers are the regionalization of semiconductor fabs and the increasing ...