How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.

IIT Madras and ISRO develop the SHAKTI microprocessor, an indigenous chip for space applications, enhancing command, control, ...

A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...

The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and ...

NCSC CTO Ollie Whitehouse discussed a UK government-backed project designed to secure underlying computer hardware, ...

IIT Madras develops indigenous Shakti semiconductor chip for ISRO, marking a milestone in Make in India efforts.

RISC C.I.C. – the open silicon ecosystem organisation – based in Cambridge has revealed a significant scale-up in a ...

The IRIS (Indigenous RISC-V Controller for Space Applications) chip was developed by IIT Madras in collaboration with ISRO’s ...

Madras and ISRO have developed an indigenous microprocessor for space applications which can be used in command and control ...

IIT Madras and ISRO developed and tested the SHAKTI-based IRIS chip for aerospace applications, promoting indigenized ...

IIT Madras and ISRO have collaboratively developed the SHAKTI microprocessor for space applications. This indigenous chip, based on RISC-V architecture and backed by the Ministry of Electronics, aims ...

CHERIoT-Ibex pipeline with specification installed using a pipeline follower Prof. Tom Melham and Louis-Emile Ploix of the University of Oxford, and Alasdair Armstrong of the University of Cambridge, ...