Semiconductor Engineering3h
Research Bits: Oct. 1
Rust-resistant coating for 2D semiconductors; polymeric material for data storage and encryption; quantum-secure deep ...
Semiconductor Engineering1d
Data Routing In Heterogeneous Chip Designs
Ensuring data gets to where it’s supposed to go at exactly the right time is a growing challenge for design engineers and ...
Semiconductor Engineering1d
Barriers To Chiplet Sockets
Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time ...
Semiconductor Engineering5d
UMI Can Scale the Memory Wall
UMI to OCP as an extension to the BoW standard. While the improvements in processor performance to enable the incredible ...
Semiconductor Engineering5d
Using AI To Glue Disparate IC Ecosystem Data
Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need to ...
Semiconductor Engineering6d
Optimizing Wafer Edge Processes For Chip Stacking
Several critical processes address wafer flatness, wafer edge defects and what's needed to enable bonded wafer stacks.
Semiconductor Engineering4d
Dualtronics: Photonic Devices on the Cation Face and Electronic Devices on the Anion Face of the Same Wafer
A new technical paper titled “Using both faces of polar semiconductor wafers for functional devices” was published by ...
Semiconductor Engineering11d
How Die Dimensions Challenge Assembly Processes
Chiplet-based products must accommodate small differences in die size and bump pitch, placing new demands on manufacturing ...
Semiconductor Engineering3d
Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
A new technical paper titled “Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs” was ...
Semiconductor Engineering7d
Models for Both Strained and Unstrained GAA FETs Using Neural Networks
A new technical paper titled “Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural ...
Semiconductor Engineering4d
Hardware Acceleration Approach for KAN Via Algorithm-Hardware Co-Design
A new technical paper titled “Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference” was ...
Semiconductor Engineering11d
New Materials Are in High Demand
Development methodologies combine old and new techniques, but getting any new material into high-volume manufacturing is a ...