EDN

RTL approach supports memory BIST and repair insertion

SOC (system-on-chip) designs often incorporate multiple instantiations of various types of memories, including single-port, double-port, and content-addressable memories of various sizes and cuts. In ...
EDN

STMicroelectronics’ design kit has memory BIST/repair

STMicroelectronics has released Atrenta's SpyGlass-MBIST (memory built-in self test) insertion solution as part of its front-end design kit. This kit is accessible to all ST design teams worldwide as ...
Semiconductor Engineering

Machine Learning Based MBIST Area Estimation

Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect ...
Design-Reuse

An Effective SRAM Repair Strategy Based on eMemory NeoFuse OTP and Siemens Tessent™ MemoryBIST

In advanced process nodes, the severe decoupling between SRAM scaling stagnation and logic circuit scaling, combined with the surging on-chip memory demands from Large Language Model (LLM) training ...
Design-Reuse

Dolphin Technology Endorses Magma's Advanced Memory BIST Solution within Blast DFT

Blast DFT complements Dolphin's advanced memory technology for demonstrably significant yield gains and ease of integration SANTA CLARA, Calif. and SAN JOSE, Calif. -- April 11, 2005-- Magma(R) Design ...