The landscape of IC design is experiencing a profound transformation. With the physical and economic limits of conventional two-dimensional scaling, the industry is rapidly embracing three-dimensional ...
The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test ...
SANTA CLARA, Calif.–During a conference call here on Tuesday, Intel Corp. unveiled what it called a “one-generation ahead” chip-manufacturing strategy designed to keep the microprocessor giant one ...
Recently, my colleague Robert Ruiz described a new approach to scan test that utilizes the high-speed I/O (HSIO) ports that exist on most chips. The benefits of this new approach include reduced test ...
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